Speaker
Description
Elettra 2.0 control system will consolidate time-critical acquisition, processing, and actuation onto a dual HPC 512 HT core server. Using the DPDK kernel bypass, this data plane is designed to acquire Turn-by-Turn streams from 168 BPMs, 4 LLRFs and 120 BLMs, and drive about 1200 magnet power supplies at 100 kHz for RT feedback purposes, with a total of 160 Mpps data rate with a few microseconds jitter level over Ethernet. Moreover, the TbT streaming will enable the extraction of machine optics parameters continuously at up to 100 Hz rep-rate.
In order to validate the processing chain a test facility couples the real-time acquisition system connected to the real BPM electronics with a simulator running on the same machine to generate synthetic TbT data and feed the RT processing pipeline that is cross-checked with the simulator ground truth.
Commodity hardware ensures upgradability, while decades of machine physics algorithms remain in C code, accelerated through efficient, hardware-level execution.
When the bare-metal returns, the system radically simplifies and accelerates at the same time: commodity hardware below, optimized physics above, and no unearned layers in between.
| Abstract Classification | Control Architecture and Strategies |
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