Speaker
Description
The Stanford Synchrotron Radiation Lightsource (SSRL) is completing a comprehensive modernization of the SPEAR3 RF control system. The legacy system, originally designed for the PEP-II B-Factory circa 1997, has operated nearly unchanged for three decades. Its core is a custom analog RF Processor (RFP) in a VXI chassis performing I/Q feedback at approximately ±90 kHz bandwidth, supplemented by dedicated Comb Filter (CFM), Gap Voltage Feedback (GVF), and Gap Feed-Forward (GFF) analog modules. Supervisory control runs as six SNL programs on a VxWorks IOC, including a few thousand-line analog calibration sequence requiring ~20 minutes to execute. Inter-subsystem communication relies on the Allen-Bradley Data Highway+ serial bus at ~1 Hz. Interlock coordination is distributed across analog modules with no central first-fault detection and a non-functional arc detection system. All hardware platforms — VXI, CAMAC, PLC-5, SLC-500, and the obsolete Slo-Syn stepper drive chain — are past end-of-life.
The upgrade replaces the entire control electronics chain while retaining the operational RF plant: one klystron at ~800 kW driving four single-cell cavities at 476.3 MHz. Two Dimtel LLRF9/476 digital controllers replace the analog RFP: Unit 1 executes the primary vector-sum field control loop within 300 ns direct loop delay and four independent cavity tuner feedback loops; Unit 2 provides reflected-power monitoring and fast RF interlock generation. A new centralized Interface Chassis introduces first-fault detection and microsecond-scale hardware interlock coordination.
I will present the system architecture, key engineering decisions driving the transition from a monolithic analog control framework to a distributed hardware-accelerated FPGA architecture, and early commissioning experience at an operating synchrotron facility
| Abstract Classification | Control Architecture and Strategies |
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